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Applications Example

Dicing of Wafer-level CSP
 
Many wafer-level CSPs have a bonded structure of silicon and resin, and the resin stress can cause significant warping of the wafer. If dicing of a wafer-level CSP is performed using a regular single cut or step cut, the effect of this warping can easily cause cracking and chipping at the border of the resin and silicon and on the silicon cutting surface.


Process Example
DISCO's solution to this issue is two-pass, four channel cutting. First, the workpiece is half cut at the first and second channels to release the stress and reduce warpage. Then, a full cut is made on the workpiece, resulting in reduced cracking and chipping.

Fig. 1: Cracking Between Resin and Silicon Border
<Two-pass, Four Channel Cutting>
Fig. 2: Two-pass, Four Channel Cutting: Top View
Fig. 3: Two-pass, Four Channel Cutting: Side View
Photo 1: Boundary During Two-pass, Four Channel Cutting
Note: Because two-pass, four channel cutting results in less throughput, DBG is also recommended. (See the January 31, 2007 press release "DBG Processing of Wafer level-CSP".)



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